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Device Overview S12XS Family
1.4.1.2
Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM ?rmware waits for additional serial commands through the BKGD pin.
1.4.2
Power Modes
The MCU features two main low-power modes. Consult the respective section for module speci?c
behavior in system stop, system pseudo stop, and system wait mode. An important source of information
about the clock system is the Clock and Reset Generator section (CRG).
1.4.2.1
System Stop Modes
The system stop modes are entered if the CPU executes the STOP instruction unless an NVM command
is active. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into pseudo stop
mode or full stop mode. Please refer to CRG section. Asserting RESET, XIRQ, IRQ or any other interrupt
that is not masked exits system stop modes. System stop modes can be exited by CPU activity, depending
on the con?guration of the interrupt request.
If the CPU executes the STOP instruction whilst an NVM command is being processed, then the system
clocks continue running until NVM activity is completed. If a non-masked interrupt occurs within this time
then the system does not effectively enter stop mode although the STOP instruction has been executed.
1.4.2.2
Full Stop Mode
The oscillator is stopped in this mode. By default all clocks are switched off and all counters and dividers
remain frozen. The Autonomous Periodic Interrupt (API) and ATD module may be enabled to self wake
the device. A Fast wake up mode is available to allow the device to wake from Full Stop mode immediately
on the PLL internal clock without starting the oscillator clock.
1.4.2.3
Pseudo Stop Mode
In this mode the system clocks are stopped but the oscillator is still running and the real time interrupt
(RTI) and watchdog (COP), API and ATD modules may be enabled. Other peripherals are turned off. This
mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed
wake up time from this mode is signi?cantly shorter.
1.4.2.4
Wait Mode
This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU clock is switched off. All peripherals can be active in system wait mode.
For further power consumption the peripherals can individually turn off their local clocks. Asserting
RESET, XIRQ, IRQ or any other interrupt that is not masked ends system wait mode.
S12XS Family Reference Manual, Rev. 1.13
50
Freescale Semiconductor
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